With regard to clock transmission, a clock transmission circuit is conventionally known that generates a low-speed clock having a frequency of ½ to the power of m (m is a natural number) from a high-speed clock and that restores and supplies to a given circuit, a high-speed clock having a frequency of 2 to the power n (n is a natural number) from this low-speed clock (see, e.g., Japanese Laid-Open Patent Publication No. 2005-122457). A frequency-multiplying circuit is known that generates a clock having a frequency multiplied based on a clock delayed by stages of delay elements (see, e.g., Japanese Laid-Open Patent Publication No. 2010-74859). A control method is known that generates a synchronizing signal from clocks having different frequencies, to match timing to other clocks having different frequencies based on the synchronizing signal and clocks (see, e.g., Japanese Laid-Open Patent Publication No. 2000-353027).
If a first signal synchronized with a first clock is converted into a second signal having a frequency synchronized with a second clock different from the first clock, the second clock must be supplied to a circuit block executing the signal conversion process. If the second signal is further converted into a third signal having a frequency synchronized with a third clock different from the first and second clocks, the third clock must be supplied to a circuit block executing the signal conversion process.
A transmitting apparatus including such multi-stage signal processing circuits has clock resources supplying the second and third clocks described above. Therefore, the number of crystal oscillators increases, disadvantageously causing increases in circuit scale, cost, and power consumption. Such disadvantages cannot be eliminated by a conventional circuit transmitting a clock, multiplying a frequency of a clock, or controlling a timing of a clock.